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Use when creating/rewriting/reviewing embedded C for microcontrollers, drivers, firmware. Triggers automaticall...\n\nTags: c:0.0.2, driver:0.0.2, embedded:0.0.2, latest:0.0.2, riscy:0.0.2, stm32:0.0.2\n\nVersion history:\n\nv0.0.2 | 2026-04-17T14:43:09.002Z | auto\n\n- Added comprehensive coding guidelines for embedded C, focusing on production-quality code for platforms like STM32, PowerPC, RISC-V.\n- Defined detailed naming, type, struct, and error-handling conventions for all generated, rewritten, or reviewed code.\n- Specified mandatory use of separate reg.h files with structured register definitions and macros—no magic numbers, no scattered register addresses.\n- Outlined modes for code generation, rewriting (with strict preservation of original logic), and review, each with explicit multi-step workflows.\n- Included a PDCA (Plan-Do-Check-Act) workflow and a detailed checklist to ensure all outputs meet the standard.\n- Added common mistakes with clear before/after examples to guide correct implementation.\n\nArchive index:\n\nArchive v0.0.2: 10 files, 20897 bytes\n\nFiles: embedded-code-skill-arch/SKILL.md (4762b), embedded-code-skill-domains/SKILL.md (2227b), embedded-code-skill-drivers/SKILL.md (2599b), embedded-code-skill-standards/SKILL.md (2738b), README_EN.md (5754b), README_JP.md (6338b), README.md (5320b), skill-card.md (3172b), SKILL.md (11757b), _meta.json (138b)\n\nFile v0.0.2:embedded-code-skill-arch/SKILL.md\n\n---\nname: embed-code-arch\ndescription: Architecture patterns for ARM Cortex-M, ARM Cortex-A, PowerPC, SPARC V8, RISC-V. Memory barriers, interrupt handling, register access.\n---\n\n# Architecture Patterns\n\n## ARM Cortex-M (MCU)\n\n```c\n/* NVIC */\n#define NVIC_BASE   0xE000E100U\n#define NVIC_ISER(n) (*(volatile uint32_t *)(NVIC_BASE + (n) * 4U))\n\n#define NVIC_ENABLE_IRQ(irq)  do { NVIC_ISER((irq) >> 5) = (1U << ((irq) & 0x1F)); } while(0)\n\n/* Memory barriers */\n__DMB(); __DSB(); __ISB();\n\n/* ISR */\nvoid __attribute__((interrupt)) TIM2_IRQHandler(void) {\n    volatile uint32_t *irq_flag = (uint32_t *)(TIM2_BASE + FLAG_OFFSET);\n    *irq_flag = 0U;\n    g_ticks++;\n    __DSB();\n}\n```\n\n## ARM Cortex-A (SoC)\n\n```c\n/* GIC */\n#define GICD_BASE  0x1E001000U\n#define GICC_BASE  0x1E000000U\n\n/* SMP barrier */\n__asm volatile (\"dmb ish\" ::: \"memory\");\n\n/* Cache */\n__asm volatile (\"ic iallu\" ::: \"memory\");\n```\n\n## PowerPC (SoC)\n\n```c\n/* SPR access */\nstatic inline uint32_t mfspr(uint16_t spr) {\n    uint32_t val;\n    __asm volatile (\"mfspr %0, %1\" : \"=r\"(val) : \"K\"(spr));\n    return val;\n}\n\n/* Barrier */\n__asm volatile (\"msync\");\n```\n\n## SPARC V8 (Leon3)\n\n```c\n/* PSR */\nstatic inline uint32_t sparc_get_psr(void) {\n    uint32_t psr;\n    __asm volatile (\"rd %%psr, %0\" : \"=r\"(psr));\n    return psr;\n}\n\n/* Barrier */\n__asm volatile (\"stbar\");\n```\n\n## RISC-V\n\n```c\n/* CSR */\n#define CSR_MSTATUS 0x300\n#define CSR_MIE     0x304\n\nstatic inline uint32_t csrr(uint32_t csr) {\n    uint32_t val;\n    __asm volatile (\"csrr %0, %1\" : \"=r\"(val) : \"K\"(csr));\n    return val;\n}\n\n/* Barrier */\n__asm volatile (\"fence\" ::: \"memory\");\n```\n\n## Quick Ref\n\n| Arch | Barrier | Interrupt | SPR/CSR |\n|------|---------|-----------|---------|\n| Cortex-M | `__DMB()` | NVIC | N/A |\n| Cortex-A | `dmb ish` | GIC | N/A |\n| PowerPC | `msync` | PIC | `mfspr` |\n| SPARC V8 | `stbar` | INTC | `rd psr` |\n| RISC-V | `fence` | PLIC | `csrr` |\n\n## 未知架构处理\n\n如果用户提到的架构不在上述列表中:\n\n### 处理步骤\n\n1. **先尝试推断**: 根据用户描述推断架构类型\n2. **尝试网上搜索**: 如果是未知架构,使用WebSearch/WebFetch搜索该架构的基础信息\n3. **使用通用模式**: 如果无法找到信息,使用通用嵌入式C模式\n4. **与用户沟通**: 把学到的架构信息反馈给用户,确认理解是否正确\n\n### 网上搜索流程\n\n当遇到未知架构时:\n\n```\n1. 使用 WebSearch 搜索: \"<架构名> embedded C programming\"\n2. 使用 WebSearch 搜索: \"<架构名> register map memory\"\n3. 使用 WebFetch 获取该架构的官方文档或芯片手册摘要\n4. 分析搜索结果,提取:\n   - 寄存器访问模式\n   - 中断处理方式\n   - 内存屏障指令\n   - 工具链信息\n5. 把学到的信息反馈给用户确认\n```\n\n### 搜索示例\n\n| 用户提到 | 搜索关键词 |\n|----------|-----------|\n| MIPS | \"MIPS embedded C interrupt controller\" |\n| ARC | \"ARC EM or ARC HS interrupt handling\" |\n| Tensilica | \"Tensilica Xtensa register access\" |\n| Andes | \"Andes RISC-V interrupt\" |\n\n### 与用户沟通格式\n\n```markdown\n🤖 **已搜索并学习该架构**\n\n根据搜索结果,我了解到该架构的一些基础信息:\n\n| 特性 | 信息 |\n|------|------|\n| 内存屏障 | 搜索到的指令 |\n| 中断方式 | 搜索到的信息 |\n| 寄存器访问 | 搜索到的模式 |\n\n**请确认以下理解是否正确:**\n1. ...\n2. ...\n\n如果信息有误,请纠正或提供正确的信息。\n```\n\n### 通用模式 (所有架构可用)\n\n```c\n/* 通用寄存器定义 - 架构无关 */\n#define REG32(base, offset)  (*(volatile uint32_t *)((base) + (offset)))\n\n/* 通用内存屏障 - 编译器级别 */\n#define MEMORY_BARRIER()  __asm volatile(\"\" ::: \"memory\")\n\n/* 通用中断使能宏 - 假设架构提供 */\n#define ENABLE_INTERRUPTS()  /* 架构特定实现 */\n#define DISABLE_INTERRUPTS() /* 架构特定实现 */\n\n/* 通用volatile指针类型 */\ntypedef volatile uint32_t *reg_ptr_t;\n```\n\n### 提醒用户格式\n\n```markdown\n⚠️ **架构信息待确认**\n\n您提到的架构不在已知列表中。\n\n为了生成正确的代码,请提供:\n1. 架构类型 (如 MIPS, ARC, Tensilica等)\n2. 内存屏障指令\n3. 中断控制器类型\n4. 寄存器基地址\n\n或者:\n- 提供该架构的代码片段作为参考\n- 说明与已知架构的相似之处\n```\n\n### 常见架构归类 (供参考)\n\n以下是基于常见芯片的架构归类,但**不保证完全准确**:\n\n| 常见芯片 | 架构 |\n|----------|------|\n| STM32系列 | ARM Cortex-M |\n| NXP LPC, Kinetis | ARM Cortex-M |\n| GD32 | ARM Cortex-M (兆易创新,兼容STM32) |\n| i.MX6, i.MX7, STM32MP | ARM Cortex-A |\n| MPC5748, QorIQ | PowerPC |\n| FE310, SiFive | RISC-V |\n\n**重要: 如果芯片不在列表中,不要猜测架构,请用WebSearch搜索确认。**\n\nFile v0.0.2:embedded-code-skill-domains/SKILL.md\n\n---\nname: embed-code-domains\ndescription: Industry domain requirements. Aerospace (DO-178C), Military (MIL-STD), Industrial (IEC 61508), Automotive (ISO 26262).\n---\n\n# Industry Domain Requirements\n\n## Detection\n\n| Domain | Keywords |\n|--------|----------|\n| Aerospace | DO-178C, DAL, ARINC, flight |\n| Military | 1553B, SpaceWire, MIL-STD, radar |\n| Industrial | IEC 61508, SIL, PLC, SCADA |\n| Automotive | ISO 26262, ASIL, CANFD |\n\n---\n\n## Aerospace (DO-178C)\n\n**DAL Levels**: A (MC/DC 100%), B (MC/DC 100%), C (Statement/Branch)\n\n```c\n/**\n * @file navigation.c\n * @brief Navigation processing\n *\n * ### Safety Level: DAL-B ###\n * - DO-178C compliance\n * - MC/DC coverage required\n *\n * ### Software Level Database ###\n * - Req ID: NAV-001\n */\n```\n\n**Requirements**:\n- No dynamic allocation\n- Deterministic behavior\n- No recursion\n- Complexity < 10\n\n---\n\n## Military (MIL-STD-1553B)\n\n```c\n/**\n * @file missile_ctrl.c\n * @brief Missile guidance control\n *\n * ### Standards ###\n * - MIL-STD-1553B\n * - SEU protection required\n * - BIT coverage > 95%\n */\n```\n\n**Requirements**:\n- Hardware redundancy\n- SEU protection\n- BIT diagnostics\n\n---\n\n## Industrial (IEC 61508)\n\n**SIL Levels**: 1, 2, 3, 4\n\n```c\n/**\n * @file plc_comm.c\n * @brief PLC communication\n *\n * ### IEC 61508 SIL-2 ###\n * - Safe state on failure\n * - Diagnostic coverage > 90%\n */\n```\n\n**Requirements**:\n- Safe state defined\n- Watchdog supervision\n- Deterministic response\n\n---\n\n## Automotive (ISO 26262)\n\n**ASIL Levels**: A, B, C, D\n\n```c\n/**\n * @file abs_controller.c\n * @brief ABS control\n *\n * ### ASIL-B ###\n * - ISO 26262 Part 2-6\n * - SPFM > 90%, LFM > 60%\n */\n```\n\n**Requirements**:\n- ASIL decomposition\n- Hardware fault tolerance\n- Freedom from interference\n\n---\n\n## Default (General Embedded)\n\n```c\n/**\n * @file sensor_driver.c\n * @brief Temperature sensor driver\n *\n * ### Architecture ### ARM Cortex-M4\n * ### Domain ### General Embedded\n */\n```\n\nNo special safety requirements.\n\n---\n\n## Quick Ref\n\n| Domain | Standard | Level | Key |\n|--------|----------|-------|-----|\n| Aerospace | DO-178C | DAL-A/B/C | MC/DC |\n| Military | MIL-STD-1553B | - | SEU |\n| Industrial | IEC 61508 | SIL-1-4 | Safe state |\n| Automotive | ISO 26262 | ASIL-A/B | SPFM/LFM |\n\nFile v0.0.2:embedded-code-skill-drivers/SKILL.md\n\n---\nname: embed-code-drivers\ndescription: Peripheral driver templates. UART, SPI, I2C, DMA, CAN, CANFD, PWM, Ethernet, 1553B, SpaceWire, SDIO, Timer, WDT, GPIO.\n---\n\n# Driver Templates\n\n## UART\n\n```c\n#define UART_DR(base)   (*(volatile uint32_t *)((base) + 0x00U))\n#define UART_CR(base)   (*(volatile uint32_t *)((base) + 0x30U))\n#define UART_FR(base)   (*(volatile uint32_t *)((base) + 0x18U))\n\ntypedef struct {\n    uint32_t base_address;\n    uint32_t baud_rate;\n} uart_config_t;\n\ntypedef struct {\n    bool     initialized;\n    uint8_t  rx_buf[256];\n    uint16_t rx_head;\n    uint16_t rx_tail;\n} uart_handle_t;\n```\n\n## SPI\n\n```c\n#define SPI_CR1(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define SPI_SR(base)   (*(volatile uint32_t *)((base) + 0x08U))\n#define SPI_DR(base)   (*(volatile uint32_t *)((base) + 0x0CU))\n\ntypedef struct {\n    uint32_t base_address;\n    uint32_t clock_hz;\n    bool     master_mode;\n} spi_config_t;\n```\n\n## I2C\n\n```c\n#define I2C_CR1(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define I2C_DR(base)   (*(volatile uint32_t *)((base) + 0x10U))\n#define I2C_SR1(base)  (*(volatile uint32_t *)((base) + 0x14U))\n```\n\n## DMA\n\n```c\n#define DMA_CCR(base,ch)  (*(volatile uint32_t *)((base) + 0x08U + (ch) * 0x14U))\n#define DMA_CPAR(base,ch) (*(volatile uint32_t *)((base) + 0x10U + (ch) * 0x14U))\n#define DMA_CMAR(base,ch) (*(volatile uint32_t *)((base) + 0x14U + (ch) * 0x14U))\n```\n\n## CAN\n\n```c\n#define CAN_MCR(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define CAN_TSR(base)  (*(volatile uint32_t *)((base) + 0x08U))\n#define CAN_BTR(base)  (*(volatile uint32_t *)((base) + 0x1CU))\n\ntypedef struct {\n    uint32_t id;\n    uint8_t  dlc;\n    uint8_t  data[64];\n} can_msg_t;\n```\n\n## GPIO\n\n```c\n#define GPIO_MODER(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define GPIO_ODR(base)   (*(volatile uint32_t *)((base) + 0x14U))\n#define GPIO_BSRR(base)  (*(volatile uint32_t *)((base) + 0x18U))\n\ntypedef enum {\n    GPIO_MODE_INPUT = 0,\n    GPIO_MODE_OUTPUT,\n    GPIO_MODE_AF,\n    GPIO_MODE_ANALOG\n} gpio_mode_t;\n```\n\n## TIMER/WDT\n\n```c\n#define TIM_CR1(base)   (*(volatile uint32_t *)((base) + 0x00U))\n#define TIM_ARR(base)   (*(volatile uint32_t *)((base) + 0x2CU))\n#define TIM_CNT(base)   (*(volatile uint32_t *)((base) + 0x24U))\n\n#define WDT_KR(base)   (*(volatile uint32_t *)((base) + 0x00U))\n#define WDT_RLR(base)  (*(volatile uint32_t *)((base) + 0x08U))\n```\n\n## 1553B\n\n```c\ntypedef enum {\n    1553_MODE_BC = 0,\n    1553_MODE_RT = 1,\n    1553_MODE_BM = 2\n}1553_mode_t;\n\ntypedef struct {\n    uint8_t  cmd;\n    uint16_t status;\n    uint16_t data[32];\n}1553_msg_t;\n```\n\nFile v0.0.2:embedded-code-skill-standards/SKILL.md\n\n---\nname: embed-code-standards\ndescription: Embedded C coding standards reference. Naming conventions, type standards, error handling, struct/enum patterns, comment rules.\n---\n\n# Coding Standards\n\n## Naming\n\n| Element | Convention | Example |\n|---------|------------|---------|\n| Variables | snake_case | `sensor_value` |\n| Globals | g_snake_case | `g_system_ticks` |\n| Constants | SCREAMING_SNAKE | `MAX_BUFFER_SIZE` |\n| Macros | SCREAMING_SNAKE | `GPIO_MODE_INPUT` |\n| Functions | camelCase | `initUart()` |\n| Struct types | snake_case_t | `uart_config_t` |\n| Enum types | snake_case_t | `gpio_state_t` |\n| Enum values | PREFIXED_SNAKE | `GPIO_STATE_LOW` |\n| Pointers | p_snake_case | `p_rx_buffer` |\n\n## Types\n\nUse only stdint.h types:\n\n```\nuint8_t  → byte, GPIO\nuint16_t → 16-bit registers\nuint32_t → 32-bit registers\nint32_t  → signed values\nbool     → flags\n```\n\n**NEVER**: int, char, long (unless necessary)\n\n## Includes (Required)\n\n```c\n#include <stdint.h>\n#include <stdbool.h>\n#include <stddef.h>\n```\n\n## Error Handling\n\n```c\ntypedef enum {\n    EmbedCode_Ok = 0,\n    EmbedCode_ErrNullPtr = -1,\n    EmbedCode_ErrInvalidArg = -2,\n    EmbedCode_ErrTimeout = -3,\n    EmbedCode_ErrBusy = -4\n} embed_code_status_t;\n\n#define VALIDATE_NOT_NULL(ptr) \\\n    do { if ((ptr) == NULL) return EmbedCode_ErrNullPtr; } while(0)\n```\n\nEvery public function:\n- Returns `embed_code_status_t`\n- Validates NULL pointers\n- Returns specific error codes\n\n## Struct Patterns\n\n```c\n// Config - const after init\ntypedef struct {\n    uint32_t base_address;\n    uint8_t  priority;\n} peripheral_config_t;\n\n// Handle - runtime state\ntypedef struct {\n    bool                initialized;\n    peripheral_config_t config;\n} peripheral_handle_t;\n\n// State enum\ntypedef enum {\n    STATE_IDLE = 0,\n    STATE_RUNNING,\n    STATE_ERROR\n} state_t;\n```\n\n## No Dynamic Allocation\n\n**PROHIBITED**: malloc, free, calloc, realloc, new, delete, VLAs\n\n**ALWAYS**: Fixed-size buffers\n\n```c\n#define BUFFER_SIZE 256U\nuint8_t buffer[BUFFER_SIZE];\n```\n\n## Comments\n\n**语言: 优先使用中文**\n\n```c\n// ✅ 正确 - 使用中文注释,解释 WHY\nconfig |= (1U << 3);  /* 低电平有效 */\n\n// ❌ 错误 - 使用英文注释\nconfig |= (1U << 3);  /* Active-low enable */\n\n// ❌ 错误 - 解释代码本身已清楚表达的内容\ni++;  /* i 自增 */\n```\n\n**注释原则:**\n- **中文优先**: 便于团队阅读和维护\n- **解释 WHY**: 说明原因和意图,而非描述代码在做什么\n- **代码自说明**: 如果代码本身已清楚表达含义,无需注释\n\n## Quality Checklist\n\n- [ ] stdint.h types only\n- [ ] Naming correct\n- [ ] Public functions return status\n- [ ] NULL validation\n- [ ] No magic numbers\n- [ ] Comments explain WHY\n- [ ] No malloc/free\n\nFile v0.0.2:SKILL.md\n\n---\nname: embedded-code-skill\ndescription: \"Generate, rewrite, or review embedded C code. Use when creating/rewriting/reviewing embedded C for microcontrollers, drivers, firmware. Triggers automatically when user mentions: generate, create, write code, implement driver, rewrite, refactor, review, check, audit.\"\nuser-invocable: true\n---\n\n# Embedded C 代码生成规范\n\n## 概述\n\n本规范用于生成生产级嵌入式 C 代码，适用于 STM32、PowerPC、RISC-V 等平台。\n\n**核心原则**: 像嵌入式软件架构师一样思考，生成可演进、可测试、可移植的代码。\n\n---\n\n## 思维方式\n\n生成代码时必须以**嵌入式软件架构师**的思维进行:\n\n| 维度 | 要求 |\n|------|------|\n| **系统视角** | 设计可演进的系统，考虑模块边界、接口契约、依赖关系 |\n| **资源意识** | 内存精确计算缓冲区，CPU 减少中断嵌套，优化关键路径 |\n| **实时性** | ISR 应尽可能短，考虑 WCET，防范优先级反转/死锁/队列溢出 |\n| **可靠性** | 看门狗策略、异常恢复、关键数据冗余存储 |\n| **硬件无关** | 寄存器抽象为结构体，驱动与业务逻辑分离 |\n| **可测试** | 公共接口易 mock，状态机可单步测试，边界条件覆盖 |\n\n---\n\n## 编码规范\n\n### 1. 类型规范\n\n| 类型 | 用途 | 禁止 |\n|------|------|------|\n| `uint8_t` | 单字节、GPIO | `char`, `signed char` |\n| `uint16_t` | 16位寄存器 | `short`, `unsigned short` |\n| `uint32_t` | 32位寄存器、时间戳 | `int`, `long`, `unsigned int` |\n| `int32_t` | 有符号值 | - |\n| `uint64_t` | 64位数据 | - |\n| `bool` | 布尔标志 | - |\n\n**必须包含的头文件:**\n```c\n#include <stdint.h>\n#include <stdbool.h>\n#include <stddef.h>\n```\n\n### 2. 命名规范\n\n| 元素 | 格式 | 示例 |\n|------|------|------|\n| 变量 | `snake_case` | `sensor_value`, `data_count` |\n| 全局变量 | `g_snake_case` | `g_system_ticks` |\n| 常量/宏 | `SCREAMING_SNAKE` | `MAX_BUFFER_SIZE`, `SPI_CR_EN` |\n| 函数 | `camelCase` | `initUart()`, `getSensorData()` |\n| 结构体类型 | `snake_case_t` | `uart_config_t` |\n| 枚举类型 | `snake_case_t` | `gpio_state_t` |\n| 枚举值 | `PREFIXED_SNAKE` | `GPIO_STATE_LOW` |\n| 指针 | `p_snake_case` | `p_rx_buffer` |\n| 寄存器结构体 | `module_name_reg_t` | `spi_reg_t` |\n| 寄存器头文件 | `module_reg.h` | `spi_reg.h` |\n\n### 3. 错误处理\n\n所有 public 函数必须:\n\n1. 返回 `embedded_code_status_t` 枚举类型\n2. 验证所有输入指针（NULL 检查）\n3. 返回具体错误码\n\n```c\ntypedef enum {\n    EmbedCode_Ok = 0,\n    EmbedCode_ErrNullPtr = -1,\n    EmbedCode_ErrInvalidArg = -2,\n    EmbedCode_ErrTimeout = -3,\n    EmbedCode_ErrBusy = -4,\n    EmbedCode_ErrNotInit = -5\n} embedded_code_status_t;\n\n#define VALIDATE_NOT_NULL(ptr) \\\n    do { if ((ptr) == NULL) return EmbedCode_ErrNullPtr; } while(0)\n```\n\n### 4. 注释规范\n\n**注释语言: 优先使用中文**\n\n| 原则 | 说明 |\n|------|------|\n| **中文优先** | 便于团队阅读和维护 |\n| **解释 WHY** | 注释应说明原因和意图，而非描述代码在做什么 |\n| **代码自说明** | 如果代码本身已清楚表达含义，无需注释 |\n\n**Doxygen 文件头格式:**\n```c\n/**\n * @file spi_reg.h\n * @brief SPI 寄存器结构体定义\n * @author Claude Code\n * @date 2026-04-10\n */\n```\n\n**行内注释示例:**\n```c\nconfig |= SPI_CR_EN_MASK;  /* 启用 SPI，低电平有效 */\n```\n\n### 5. 寄存器结构体定义\n\n**每个外设模块必须有独立的 reg.h 文件:**\n\n| 必需元素 | 说明 |\n|----------|------|\n| `XXX_BASE_ADDR` | 基地址定义，格式：`XXX_BASE_ADDR` |\n| `xxx_reg_t` | 寄存器结构体，使用 `volatile uint32_t` |\n| `XXX_XXX_MASK/SHIFT` | 位字段宏定义 |\n| `XXX_REG` | 结构体指针访问宏 |\n\n**reg.h 模板:**\n```c\n/**\n * @file spi_reg.h\n * @brief SPI 外设寄存器定义\n */\n#ifndef SPI_REG_H\n#define SPI_REG_H\n\n#include <stdint.h>\n\n/* 基地址 */\n#define SPI_BASE_ADDR  (0xA0010000U)\n\n/* 寄存器结构体 */\ntypedef struct {\n    volatile uint32_t CTRL;     /* 0x00: 控制寄存器 */\n    volatile uint32_t STATUS;   /* 0x04: 状态寄存器 */\n    volatile uint32_t DATA;     /* 0x08: 数据寄存器 */\n} spi_reg_t;\n\n/* 位字段定义 */\n#define SPI_CTRL_EN_MASK      (1U << 0)\n#define SPI_CTRL_MODE_MASK    (3U << 2)\n\n/* 寄存器访问 */\n#define SPI_REG  ((spi_reg_t *) SPI_BASE_ADDR)\n\n#endif /* SPI_REG_H */\n```\n\n### 6. 寄存器赋值规范\n\n**禁止直接赋字面值，必须使用已定义的宏:**\n\n```c\n// ❌ 错误\nSPI_REG->CTRL = 0x47U;\nSPI_REG->BAUD = 250U;\n\n// ✅ 正确\nSPI_REG->CTRL = SPI_CTRL_INIT_VAL;\nSPI_REG->BAUD = SPI_BAUD_DIV;\n```\n\n### 7. 安全编码\n\n| 禁止 | 必须 |\n|------|------|\n| `malloc`, `free`, `calloc`, `realloc` | 固定大小缓冲区 |\n| `new`, `delete` | 环形缓冲区用于数据流 |\n| VLA (变长数组) | 精确计算的缓冲区大小 |\n\n```c\n#define BUFFER_SIZE 256U\nuint8_t buffer[BUFFER_SIZE];\n```\n\n### 8. 数据结构\n\n| 场景 | 方式 |\n|------|------|\n| 相关配置数据 | `struct` |\n| 相关常量集合 | `enum` |\n| 相关状态数据 | `struct` |\n\n```c\n/* 配置结构体 */\ntypedef struct {\n    uint32_t base_address;\n    uint16_t interrupt_priority;\n    bool     enable_dma;\n} peripheral_config_t;\n\n/* 句柄结构体 */\ntypedef struct {\n    bool                initialized;\n    peripheral_config_t config;\n} peripheral_handle_t;\n```\n\n---\n\n## 工作模式\n\n### GENERATE 模式\n\n直接应用本规范生成代码，无需保留任何旧代码。\n\n### REWRITE 模式\n\n**核心原则: 功能流程优先**\n\n> ⚠️ 用户提供的源代码代表着原有的功能实现流程。即使代码有错误，在修改前必须先完整理解其功能流程，再进行符合规范的改写。不得为符合规范而破坏原有的功能流程。\n\n**执行步骤:**\n\n| 步骤 | 内容 |\n|------|------|\n| **Step 1: 理解原代码** | 梳理数据流、识别状态机/算法、标注寄存器操作 |\n| **Step 2: 识别重写部分** | 确定需重构的函数/模块 |\n| **Step 3: 按规范重写** | 类型/命名/结构体符合规范，功能逻辑保持一致 |\n| **Step 4: 回查验证** | 验证功能流程未改变，所有规范已满足 |\n\n**关于原代码中的 bug：**\n- 原代码的 bug 属于\"功能流程\"的一部分\n- 如果 bug 是用户期望保留的行为（如已知的工作around），保持原样\n- 如果原代码有语法错误无法编译，标注问题但不擅自修复\n- 除非用户明确要求，否则不修改原代码的功能逻辑\n\n### REVIEW 模式\n\n检查现有代码是否符合嵌入式 C 规范。\n\n**执行步骤:**\n\n| 步骤 | 内容 |\n|------|------|\n| **Step 1: 对照检查** | 按回查清单逐项检查 |\n| **Step 2: 标注问题** | 列出不符合规范的地方 |\n| **Step 3: 提出建议** | 提供具体的修改建议 |\n\n---\n\n## 项目文件结构\n\n```\nproject/\n├── inc/\n│   ├── module_reg.h      # 寄存器结构体定义（每个外设必须有）\n│   ├── module_config.h   # 配置参数\n│   └── module.h          # 公共接口\n└── src/\n    └── module.c          # 实现\n```\n\n---\n\n## PDCA 工作流\n\n```\n┌─────────────────────────────────────────────────────────┐\n│  P (Plan) - 分析需求，检查完备性                         │\n│    • 确定模式: GENERATE / REWRITE / REVIEW              │\n│    • 检测领域/架构/外设关键词                            │\n│    • 检查关键信息是否完备（基地址等）                     │\n│    ⚡ REWRITE模式: 优先理解原代码功能流程                │\n├─────────────────────────────────────────────────────────┤\n│  D (Do) - 生成/重写代码                                 │\n│    • GENERATE: 直接应用本规范                           │\n│    • REWRITE: 保持原功能流程，应用本规范                 │\n│    • 创建或更新 reg.h 寄存器结构体定义                   │\n│    • 生成符合规范的代码                                  │\n├─────────────────────────────────────────────────────────┤\n│  C (Check) - 回查验证                                   │\n│    • 对照回查清单逐项检查                               │\n│    • 验证寄存器结构体定义是否正确                        │\n│    ⚡ REWRITE模式: 验证功能流程是否保持一致             │\n├─────────────────────────────────────────────────────────┤\n│  A (Act) - 修正输出                                     │\n│    • 修正所有发现的问题                                  │\n│    • 重新回查确认                                       │\n│    • 输出合格代码                                        │\n└─────────────────────────────────────────────────────────┘\n```\n\n---\n\n## 回查清单\n\n生成后必须逐项检查:\n\n| # | 检查项 | 不合格则修正 |\n|---|--------|------------|\n| 1 | 是否有对应的 reg.h 文件? | 创建 reg.h |\n| 2 | 寄存器是否用 `volatile uint32_t` 结构体定义? | 重构为结构体 |\n| 3 | 位字段是否有宏定义 (MASK/SHIFT)? | 添加位字段宏 |\n| 4 | 类型是否仅用 stdint.h? | 替换所有非标准类型 |\n| 5 | 命名是否符合规范表? | 修正所有命名 |\n| 6 | 所有 public 函数有错误处理? | 添加状态返回 |\n| 7 | 无任何 malloc/free/VLA? | 替换为固定缓冲区 |\n| 8 | 注释是否使用中文? | 重写注释 |\n| 9 | 文件头是否完整 (Doxygen)? | 添加 Doxygen |\n| 10 | 生成的代码是否符合规范? | 修正生成代码 |\n| ⚡ 11 | REWRITE 模式: 原代码的功能流程是否保持一致? | 确保数据流/状态机/算法逻辑不变 |\n| ⚡ 12 | 寄存器赋值是否都使用宏? | 添加宏定义，禁止字面值赋值 |\n\n---\n\n## 常见错误\n\n### 错误 1: 寄存器定义散落各处\n\n```c\n// ❌ 错误\n#define SPI_CTRL_ADDR  (*(volatile uint32_t *)0xA0010000)\nvoid spiInit(void) { SPI_CTRL_ADDR = 0x47; }\n\n// ✅ 正确 - 独立的 reg.h，统一的命名风格\n#include \"spi_reg.h\"\nvoid spiInit(void) { SPI_REG->CTRL = SPI_CTRL_INIT_VAL; }\n```\n\n### 错误 2: 魔法数字\n\n```c\n// ❌ 错误 - 含义不清\nif (SPI_REG->STATUS & 0x04) { }\nSPI_REG->CTRL |= (1U << 7);\n\n// ✅ 正确 - 命名位字段宏\nif (SPI_REG->STATUS & SPI_STATUS_TF_EMPT_MASK) { }  /* TX FIFO empty */\nSPI_REG->CTRL |= SPI_CTRL_SCPOL_MASK;               /* 时钟极性 */\n```\n\n### 错误 3: 使用 `__I`/`__IO` 前缀\n\n```c\n// ❌ 错误 - ARM CMSIS 特有，不具可移植性\ntypedef struct {\n    __I uint32_t DATA;\n    __IO uint32_t CTRL;\n} spi_reg_t;\n\n// ✅ 正确 - 标准 volatile\ntypedef struct {\n    volatile uint32_t DATA;\n    volatile uint32_t CTRL;\n} spi_reg_t;\n```\n\n### 错误 4: 直接赋字面值\n\n```c\n// ❌ 错误 - 魔法数字\nSPI_REG->BAUD = 250U;\nSPI_REG->CTRL = 0x08U;\n\n// ✅ 正确 - 使用宏定义\nSPI_REG->BAUD = SPI_BAUD_DIV;\nSPI_REG->CTRL = SPI_CTRL_INIT_VAL;\n```\n\n---\n\n## 输出格式\n\nGENERATE 模式输出每个外设模块:\n\n```\nmodule/\n├── module_reg.h    # 寄存器结构体定义\n├── module.h        # 公共接口\n└── module.c       # 实现\n```\n\nFile v0.0.2:README.md\n\n# embedded-code-skill\n\n> 嵌入式 C 代码生成规范 — 统一团队代码风格，生成生产级驱动代码\n\n<!-- Language Switcher -->\n[简体中文](README.md) · [English](README_EN.md) · [日本語](README_JP.md)\n\n---\n\n[![Platform: Claude Code | VS Code | Cursor | OpenClaw | Hermes Agent](https://img.shields.io/badge/Platform-Claude%20Code%20%7C%20VS%20Code%20%7C%20Cursor%20%7C%20OpenClaw%20%7C%20Hermes%20Agent-blue)]()\n[![Standard: MISRA-C Compliant](https://img.shields.io/badge/Standard-MISRA--C%20Compliant-green)]()\n[![License: MIT](https://img.shields.io/badge/License-MIT-yellow)]()\n\n---\n\n## 特性\n\n- **三种工作模式** — GENERATE（生成）、REWRITE（重写）、REVIEW（审查）\n- **生产级代码** — 像嵌入式软件架构师一样思考，生成可演进、可测试的代码\n- **多平台支持** — STM32 (Cortex-M)、PowerPC、RISC-V、ARM Cortex-A\n- **团队统一** — 代码风格一致，review 有据可依\n- **自我进化** — 内置达尔文式优化系统，持续改进规范质量\n\n---\n\n## 快速开始\n\n```bash\n/embedded-code-skill 生成一个STM32 UART驱动，基地址 0x4000C000\n/embedded-code-skill 重写这段代码为符合规范的版本\n/embedded-code-skill 审查这段代码是否符合规范\n```\n\n---\n\n## 三种工作模式\n\n### GENERATE 模式\n\n直接应用规范生成代码，无需保留任何旧代码。\n\n### REWRITE 模式\n\n**核心原则: 功能流程优先**\n\n- 用户提供的源代码代表着原有的功能实现流程\n- 即使代码有错误，也必须先完整理解其功能流程再改写\n- 不得为符合规范而破坏原有的功能逻辑\n- 原代码的 bug 属于\"功能流程\"的一部分，默认保持原样\n\n### REVIEW 模式\n\n检查现有代码是否符合嵌入式 C 规范，按回查清单逐项检查并提出修改建议。\n\n---\n\n## 核心要求\n\n| 要求 | 规范 |\n|------|------|\n| **可读性** | `snake_case` / `SCREAMING_SNAKE` / `camelCase` 命名，Doxygen 注释，中文优先 |\n| **可移植性** | `stdint.h` 类型，`volatile` 寄存器宏，无 `int`/`char`/`long` |\n| **数据结构** | `struct`/`enum` 组织数据，无散落全局变量 |\n| **错误处理** | public 函数返回 `embedded_code_status_t`，NULL 检查 |\n| **安全编码** | 禁止 `malloc`/`free`/VLA，固定大小缓冲区 |\n\n---\n\n## 生成代码前请提供\n\n| 信息 | 必要性 | 示例 |\n|------|--------|------|\n| 外设寄存器基地址 | **必需** | `UART_BASE_ADDR = 0x4000C000U` |\n| 芯片/架构类型 | 可推断 | `STM32`, `Cortex-M4`, `RISC-V` |\n\n> **注意**: 基地址必须提供，禁止 AI 编造寄存器地址。\n\n---\n\n## 文件结构\n\n```\nembedded-code-skill/\n├── SKILL.md                     # 斜杠命令入口\n├── README.md                    # 本文档\n│\n├── .evolution/                  # 自我进化系统\n│   ├── SKILL.md                # 进化系统主文件\n│   ├── test-prompts.json       # 测试用例集\n│   ├── results.tsv             # 优化历史记录\n│   └── README.md               # 进化系统说明\n│\n├── embedded-code-skill-standards/        # 编码标准详情\n│   └── SKILL.md\n│\n├── embedded-code-skill-arch/             # 架构模式\n│   └── SKILL.md                # Cortex-M/A, PowerPC, RISC-V\n│\n├── embedded-code-skill-drivers/          # 驱动模板\n│   └── SKILL.md                # UART, SPI, I2C, DMA, CAN\n│\n└── embedded-code-skill-domains/          # 领域规范\n    └── SKILL.md                # 航天/军工/工业/汽车\n```\n\n---\n\n## 输出格式\n\nGENERATE 模式输出每个外设模块：\n\n```\nmodule/\n├── module_reg.h    # 寄存器结构体定义\n├── module.h        # 公共接口\n└── module.c       # 实现\n```\n\n**uart_reg.h 示例:**\n\n```c\n/**\n * @file uart_reg.h\n * @brief UART 外设寄存器定义\n */\n#ifndef UART_REG_H\n#define UART_REG_H\n\n#include <stdint.h>\n\n/* 基地址 */\n#define UART_BASE_ADDR  (0x4000C000U)\n\n/* 寄存器结构体 */\ntypedef struct {\n    volatile uint32_t DR;       /* 0x00: Data register */\n    volatile uint32_t RSR;      /* 0x04: Receive status register */\n    volatile uint32_t Reserved;\n    volatile uint32_t FR;       /* 0x18: Flag register */\n    volatile uint32_t IBRD;     /* 0x24: Integer baud rate divisor */\n    volatile uint32_t FBRD;     /* 0x28: Fractional baud rate divisor */\n    volatile uint32_t LCRH;     /* 0x2C: Line control register */\n    volatile uint32_t CR;       /* 0x30: Control register */\n} uart_reg_t;\n\n/* 寄存器访问 */\n#define UART_REG  ((uart_reg_t *) UART_BASE_ADDR)\n\n#endif /* UART_REG_H */\n```\n\n---\n\n## 自我进化系统\n\n内置自我优化系统：\n\n- **8维度评估** — 结构质量（60分）+ 实际效果（40分）\n- **棘轮机制** — 只保留改进，自动回滚退步\n- **子 agent 验证** — 效果维度必须用子 agent 执行\n- **人在回路** — 每轮优化后暂停等待用户确认\n\n### 触发进化\n\n```\n用户：\"优化 embedded-code-skill\"      → 完整优化流程\n用户：\"评估 embedded-code-skill 质量\"  → 仅评估不优化\n用户：\"运行 embedded-code-skill 自我进化\" → 自动优化直到确认\n```\n\n---\n\n## 贡献\n\n欢迎提交 Issue 和 Pull Request！\n\n---\n\n## 许可\n\nMIT License\n\nFile v0.0.2:_meta.json\n\n{\n  \"ownerId\": \"kn7166gr1dchsr9wbhdbp93qzh850x9z\",\n  \"slug\": \"embedded-code-skill\",\n  \"version\": \"0.0.2\",\n  \"publishedAt\": 1776436989002\n}\n\nFile v0.0.2:README_EN.md\n\n# embedded-code-skill\n\n> Embedded C Code Generation Specification — Unified team code style, generate production-grade driver code\n\n<!-- Language Switcher -->\n[简体中文](README.md) · [English](README_EN.md) · [日本語](README_JP.md)\n\n---\n\n[![Platform: Claude Code | VS Code | Cursor | OpenClaw | Hermes Agent](https://img.shields.io/badge/Platform-Claude%20Code%20%7C%20VS%20Code%20%7C%20Cursor%20%7C%20OpenClaw%20%7C%20Hermes%20Agent-blue)]()\n[![Standard: MISRA-C Compliant](https://img.shields.io/badge/Standard-MISRA--C%20Compliant-green)]()\n[![License: MIT](https://img.shields.io/badge/License-MIT-yellow)]()\n\n---\n\n## Features\n\n- **Three Work Modes** — GENERATE, REWRITE, REVIEW\n- **Production-Grade Code** — Think like an embedded software architect, generate evolvable and testable code\n- **Multi-Platform** — STM32 (Cortex-M), PowerPC, RISC-V, ARM Cortex-A\n- **Team Uniformity** — Consistent code style, review with evidence\n- **Self-Evolution** — Built-in Darwin-style optimization system, continuous improvement\n\n---\n\n## Quick Start\n\n```bash\n/embedded-code-skill Generate an STM32 UART driver, base address 0x4000C000\n/embedded-code-skill Rewrite this code to conform to the specification\n/embedded-code-skill Review if this code conforms to the specification\n```\n\n---\n\n## Three Work Modes\n\n### GENERATE Mode\n\nGenerate code directly using the specification, no need to preserve old code.\n\n### REWRITE Mode\n\n**Core Principle: Function Flow First**\n\n- User-provided source code represents the original functional implementation flow\n- Even if code has errors, you must fully understand its functional flow before rewriting\n- Never破坏 the original functional logic to conform to the specification\n- Bugs in the original code are part of the \"functional flow\" and are kept by default\n\n### REVIEW Mode\n\nCheck if existing code conforms to the Embedded C specification, check item by item against the review checklist and provide modification suggestions.\n\n---\n\n## Core Requirements\n\n| Requirement | Specification |\n|------------|----------------|\n| **Readability** | `snake_case` / `SCREAMING_SNAKE` / `camelCase` naming, Doxygen comments |\n| **Portability** | `stdint.h` types, `volatile` register macros, no `int`/`char`/`long` |\n| **Data Structure** | `struct`/`enum` for data organization, no scattered global variables |\n| **Error Handling** | Public functions return `embedded_code_status_t`, NULL checks |\n| **Safe Coding** | No `malloc`/`free`/VLA, fixed-size buffers |\n\n---\n\n## Required Information Before Code Generation\n\n| Information | Necessity | Example |\n|-------------|----------|---------|\n| Peripheral register base address | **Required** | `UART_BASE_ADDR = 0x4000C000U` |\n| Chip/Architecture type | Inferable | `STM32`, `Cortex-M4`, `RISC-V` |\n\n> **Note**: Base address must be provided, AI must not fabricate register addresses.\n\n---\n\n## File Structure\n\n```\nembedded-code-skill/\n├── SKILL.md                     # Slash command entry\n├── README.md                    # This file (Chinese)\n├── README_EN.md                 # English version\n├── README_JP.md                 # Japanese version\n│\n├── .evolution/                  # Self-evolution system\n│   ├── SKILL.md                # Evolution system main file\n│   ├── test-prompts.json       # Test case set\n│   ├── results.tsv            # Optimization history\n│   └── README.md               # Evolution system docs\n│\n├── embedded-code-skill-standards/\n│   └── SKILL.md\n│\n├── embedded-code-skill-arch/\n│   └── SKILL.md                # Cortex-M/A, PowerPC, RISC-V\n│\n├── embedded-code-skill-drivers/\n│   └── SKILL.md                # UART, SPI, I2C, DMA, CAN\n│\n└── embedded-code-skill-domains/\n    └── SKILL.md                # Aerospace/Military/Industrial/Automotive\n```\n\n---\n\n## Output Format\n\nGENERATE mode outputs each peripheral module:\n\n```\nmodule/\n├── module_reg.h    # Register structure definition\n├── module.h        # Public interface\n└── module.c       # Implementation\n```\n\n**uart_reg.h Example:**\n\n```c\n/**\n * @file uart_reg.h\n * @brief UART peripheral register definition\n */\n#ifndef UART_REG_H\n#define UART_REG_H\n\n#include <stdint.h>\n\n/* Base address */\n#define UART_BASE_ADDR  (0x4000C000U)\n\n/* Register structure */\ntypedef struct {\n    volatile uint32_t DR;       /* 0x00: Data register */\n    volatile uint32_t RSR;      /* 0x04: Receive status register */\n    volatile uint32_t Reserved;\n    volatile uint32_t FR;       /* 0x18: Flag register */\n    volatile uint32_t IBRD;     /* 0x24: Integer baud rate divisor */\n    volatile uint32_t FBRD;     /* 0x28: Fractional baud rate divisor */\n    volatile uint32_t LCRH;     /* 0x2C: Line control register */\n    volatile uint32_t CR;       /* 0x30: Control register */\n} uart_reg_t;\n\n/* Register access */\n#define UART_REG  ((uart_reg_t *) UART_BASE_ADDR)\n\n#endif /* UART_REG_H */\n```\n\n---\n\n## Self-Evolution System\n\nBuilt-in self-optimization system based on Darwin.skill:\n\n- **8-Dimension Evaluation** — Structural quality (60pts) + Actual effect (40pts)\n- **Ratchet Mechanism** — Only keep improvements, auto-rollback on regression\n- **Sub-agent Verification** — Effect dimensions must use sub-agents\n- **Human-in-the-Loop** — Pause after each optimization round for user confirmation\n\n### Trigger Evolution\n\n```\nUser: \"Optimize embedded-code-skill\"           → Full optimization flow\nUser: \"Evaluate embedded-code-skill quality\"  → Evaluation only\nUser: \"Run embedded-code-skill self-evolution\" → Auto-optimize until confirmed\n```\n\n---\n\n## Contributing\n\nIssues and Pull Requests are welcome!\n\n---\n\n## License\n\nMIT License\n\nFile v0.0.2:README_JP.md\n\n# embedded-code-skill\n\n> Embedded C コード生成仕様 — チームコードスタイルの統一、プロダクショングレードのドライバコード生成\n\n<!-- Language Switcher -->\n[简体中文](README.md) · [English](README_EN.md) · [日本語](README_JP.md)\n\n---\n\n[![Platform: Claude Code | VS Code | Cursor | OpenClaw | Hermes Agent](https://img.shields.io/badge/Platform-Claude%20Code%20%7C%20VS%20Code%20%7C%20Cursor%20%7C%20OpenClaw%20%7C%20Hermes%20Agent-blue)]()\n[![Standard: MISRA-C Compliant](https://img.shields.io/badge/Standard-MISRA--C%20Compliant-green)]()\n[![License: MIT](https://img.shields.io/badge/License-MIT-yellow)]()\n\n---\n\n## 機能\n\n- **3つの動作モード** — GENERATE（生成）、REWRITE（書き換え）、REVIEW（レビュー）\n- **プロダクショングレードのコード** — 組込みソフトウェアアーキテクトのように考え、進化可能でテスト可能なコードを生成\n- **マルチプラットフォーム** — STM32 (Cortex-M)、PowerPC、RISC-V、ARM Cortex-A\n- **チーム統一** — 一貫したコードスタイル、レビューエビデンス\n- **自己進化** — 組込みのダーウィン式最適化システム、継続的な改善\n\n---\n\n## クイックスタート\n\n```bash\n/embedded-code-skill STM32 UARTドライバを生成、ベースアドレス 0x4000C000\n/embedded-code-skill このコードを仕様に合わせて書き換える\n/embedded-code-skill このコードが仕様是否符合をレビュー\n```\n\n---\n\n## 3つの動作モード\n\n### GENERATE モード\n\n仕様を直接適用してコードを生成。古いコードの保持は不要。\n\n### REWRITE モード\n\n**核心原則：機能フローファースト**\n\n- ユーザーが提供したソースコードは元の機能実装フローを表す\n- コードにエラーがあっても、書き換える前に機能フローを完全に理解する必要がある\n- 仕様に合わせるために元の機能ロジックを壊してはならない\n- 元コードのバグは「機能フロー」の一部であり、デフォルトで維持\n\n### REVIEW モード\n\n既存のコードが Embedded C 仕様に是否符合かをチェックし、レビューリストに従って項目ごとにチェックし、変更提案を提供。\n\n---\n\n## コア要件\n\n| 要件 | 仕様 |\n|------|------|\n| **可読性** | `snake_case` / `SCREAMING_SNAKE` / `camelCase` 命名、Doxygenコメント |\n| **移植性** | `stdint.h` タイプ、`volatile` レジスタマクロ、`int`/`char`/`long` 禁止 |\n| **データ構造** | `struct`/`enum` でデータ組織、散らばったグローバル変数禁止 |\n| **エラー処理** | public関数は `embedded_code_status_t` を返す、NULL チェック |\n| **安全なコーディング** | `malloc`/`free`/VLA 禁止、固定サイズバッファ |\n\n---\n\n## コード生成前に提供する情報\n\n| 情報 | 必要性 | 例 |\n|------|--------|-----|\n| 外周レジスタベースアドレス | **必須** | `UART_BASE_ADDR = 0x4000C000U` |\n| チップ/アーキテクチャタイプ | 推論可能 | `STM32`, `Cortex-M4`, `RISC-V` |\n\n> **注意**: ベースアドレスは必須。AIはレジスタアドレスを捏造してはならない。\n\n---\n\n## ファイル構造\n\n```\nembedded-code-skill/\n├── SKILL.md                     # スラッシュコマンドエントリ\n├── README.md                    # このファイル（中国語）\n├── README_EN.md                 # 英語版\n├── README_JP.md                # 日本語版\n│\n├── .evolution/                  # 自己進化システム\n│   ├── SKILL.md                # 進化システムメインファイル\n│   ├── test-prompts.json       # テストケースセット\n│   ├── results.tsv            # 最適化履歴\n│   └── README.md              # 進化システム文書\n│\n├── embedded-code-skill-standards/\n│   └── SKILL.md\n│\n├── embedded-code-skill-arch/\n│   └── SKILL.md                # Cortex-M/A, PowerPC, RISC-V\n│\n├── embedded-code-skill-drivers/\n│   └── SKILL.md                # UART, SPI, I2C, DMA, CAN\n│\n└── embedded-code-skill-domains/\n    └── SKILL.md                # 航空/軍事/産業/自動車\n```\n\n---\n\n## 出力形式\n\nGENERATE モードは各外周モジュールを出力：\n\n```\nmodule/\n├── module_reg.h    # レジスタ構造体定義\n├── module.h        # 公開インターフェース\n└── module.c       # 実装\n```\n\n**uart_reg.h 例:**\n\n```c\n/**\n * @file uart_reg.h\n * @brief UART 外周レジスタ定義\n */\n#ifndef UART_REG_H\n#define UART_REG_H\n\n#include <stdint.h>\n\n/* ベースアドレス */\n#define UART_BASE_ADDR  (0x4000C000U)\n\n/* レジスタ構造体 */\ntypedef struct {\n    volatile uint32_t DR;       /* 0x00: Data register */\n    volatile uint32_t RSR;      /* 0x04: Receive status register */\n    volatile uint32_t Reserved;\n    volatile uint32_t FR;       /* 0x18: Flag register */\n    volatile uint32_t IBRD;     /* 0x24: Integer baud rate divisor */\n    volatile uint32_t FBRD;     /* 0x28: Fractional baud rate divisor */\n    volatile uint32_t LCRH;     /* 0x2C: Line control register */\n    volatile uint32_t CR;       /* 0x30: Control register */\n} uart_reg_t;\n\n/* レジスタアクセス */\n#define UART_REG  ((uart_reg_t *) UART_BASE_ADDR)\n\n#endif /* UART_REG_H */\n```\n\n---\n\n## 自己進化システム\n\nダーウィン.skillに基づく組込み自己最適化システム：\n\n- **8次元評価** — 構造品質（60点）+ 実際効果（40点）\n- **ラチェット機構** — 改善のみ保持、自動的にロールバック\n- **サブエージェント検証** — 効果次元はサブエージェントを使用する必要がある\n- **人在ループ** — 各最適化ラウンド後に一時停止、ユーザーの確認待ち\n\n### 進化をトリガー\n\n```\nユーザー：「embedded-code-skillを最適化」           → 完全な最適化フロー\nユーザー：「embedded-code-skillの品質を評価」      → 評価のみ\nユーザー：「embedded-code-skillの自己進化を実行」  → 確認まで自動最適化\n```\n\n---\n\n## 貢献\n\nIssue と Pull Request を歓迎！\n\n---\n\n## ライセンス\n\nMIT License\n\nFile v0.0.2:skill-card.md\n\n## Description:\n\nGenerate, rewrite, or review embedded C code for microcontrollers, drivers, and firmware.\n\nThis skill is ready for commercial/non-commercial use.\n\n## Publisher:\n\n[leon-2050](https://clawhub.ai/user/leon-2050)\n\n### License/Terms of Use:\n\nMIT-0\n\n## Use Case:\n\nDevelopers and firmware engineers use this skill to generate, rewrite, or review embedded C modules, including register definitions, peripheral drivers, coding-standard checks, and platform-specific guidance for MCU and SoC targets.\n\n### Deployment Geography for Use:\n\nGlobal\n\n## Known Risks and Mitigations:\n\nRisk: The skill can broadly auto-trigger on common code-generation and review language, which may make it active outside intentional embedded C tasks.\n\nMitigation: Limit activation to explicit embedded C, firmware, driver, or microcontroller requests before installing it in a shared agent environment.\n\nRisk: The rewrite workflow preserves original functional behavior by default, so existing safety or security defects in firmware may be carried forward.\n\nMitigation: Tell the agent whether to preserve behavior exactly or fix identified safety and security defects, then require human review of rewritten firmware.\n\nRisk: Generated embedded code may affect hardware control, safety functions, or regulated compliance work.\n\nMitigation: Require domain review, hardware validation, and compliance checks before using generated code in safety-critical, industrial, automotive, aerospace, or military systems.\n\nRisk: Architecture lookup and self-optimization behavior may use external research or alter skill behavior if enabled.\n\nMitigation: Require explicit approval before web research or self-optimization, and review any resulting guidance or skill changes before use.\n\nRisk: Incorrect or missing peripheral base addresses can produce invalid firmware register access.\n\nMitigation: Require users to provide authoritative base addresses or chip documentation, and reject or escalate requests that would require fabricating register addresses.\n\n## Reference(s):\n\n- [ClawHub Skill Page](https://clawhub.ai/leon-2050/skills/embedded-code-skill)\n- [English README](artifact/README_EN.md)\n- [Primary Skill Definition](artifact/SKILL.md)\n- [Coding Standards Reference](artifact/embedded-code-skill-standards/SKILL.md)\n- [Architecture Patterns](artifact/embedded-code-skill-arch/SKILL.md)\n- [Driver Templates](artifact/embedded-code-skill-drivers/SKILL.md)\n- [Industry Domain Requirements](artifact/embedded-code-skill-domains/SKILL.md)\n\n## Skill Output:\n\n**Output Type(s):** [code, markdown, guidance]\n\n**Output Format:** [Markdown with embedded C code blocks and review findings]\n\n**Output Parameters:** [1D]\n\n**Other Properties Related to Output:** [May propose module-level files such as module_reg.h, module.h, and module.c.]\n\n## Skill Version(s):\n\n0.0.2 (source: server release metadata, created 2026-04-17T14:43:09Z)\n\n## Ethical Considerations:\n\nUsers should evaluate whether this skill is appropriate for their environment, review any generated or modified files before relying on them, and apply their organization's safety, security, and compliance requirements before deployment.","readmeExcerpt":"Skill: Embedded Code Skill Owner: leon-2050 Summary: Generate, rewrite, or review embedded C code. Use when creating/rewriting/reviewing embedded C for microcontrollers, drivers, firmware. Triggers automaticall... Tags: c:0.0.2, driver:0.0.2, embedded:0.0.2, latest:0.0.2, riscy:0.0.2, stm32:0.0.2 Version history: v0.0.2 | 2026-04-17T14:43:09.002Z | auto - Added comprehensive coding guidelines for embedded C, focusing","codeSnippets":[],"executableExamples":[{"language":"c","snippet":"/* NVIC */\n#define NVIC_BASE   0xE000E100U\n#define NVIC_ISER(n) (*(volatile uint32_t *)(NVIC_BASE + (n) * 4U))\n\n#define NVIC_ENABLE_IRQ(irq)  do { NVIC_ISER((irq) >> 5) = (1U << ((irq) & 0x1F)); } while(0)\n\n/* Memory barriers */\n__DMB(); __DSB(); __ISB();\n\n/* ISR */\nvoid __attribute__((interrupt)) TIM2_IRQHandler(void) {\n    volatile uint32_t *irq_flag = (uint32_t *)(TIM2_BASE + FLAG_OFFSET);\n    *irq_flag = 0U;\n    g_ticks++;\n    __DSB();\n}"},{"language":"c","snippet":"/* GIC */\n#define GICD_BASE  0x1E001000U\n#define GICC_BASE  0x1E000000U\n\n/* SMP barrier */\n__asm volatile (\"dmb ish\" ::: \"memory\");\n\n/* Cache */\n__asm volatile (\"ic iallu\" ::: \"memory\");"},{"language":"c","snippet":"/* SPR access */\nstatic inline uint32_t mfspr(uint16_t spr) {\n    uint32_t val;\n    __asm volatile (\"mfspr %0, %1\" : \"=r\"(val) : \"K\"(spr));\n    return val;\n}\n\n/* Barrier */\n__asm volatile (\"msync\");"},{"language":"c","snippet":"/* PSR */\nstatic inline uint32_t sparc_get_psr(void) {\n    uint32_t psr;\n    __asm volatile (\"rd %%psr, %0\" : \"=r\"(psr));\n    return psr;\n}\n\n/* Barrier */\n__asm volatile (\"stbar\");"},{"language":"c","snippet":"/* CSR */\n#define CSR_MSTATUS 0x300\n#define CSR_MIE     0x304\n\nstatic inline uint32_t csrr(uint32_t csr) {\n    uint32_t val;\n    __asm volatile (\"csrr %0, %1\" : \"=r\"(val) : \"K\"(csr));\n    return val;\n}\n\n/* Barrier */\n__asm volatile (\"fence\" ::: \"memory\");"},{"language":"text","snippet":"1. 使用 WebSearch 搜索: \"<架构名> embedded C programming\"\n2. 使用 WebSearch 搜索: \"<架构名> register map memory\"\n3. 使用 WebFetch 获取该架构的官方文档或芯片手册摘要\n4. 分析搜索结果,提取:\n   - 寄存器访问模式\n   - 中断处理方式\n   - 内存屏障指令\n   - 工具链信息\n5. 把学到的信息反馈给用户确认"}],"parameters":null,"dependencies":[],"permissions":[],"extractedFiles":[{"path":"embedded-code-skill-arch/SKILL.md","content":"---\nname: embed-code-arch\ndescription: Architecture patterns for ARM Cortex-M, ARM Cortex-A, PowerPC, SPARC V8, RISC-V. Memory barriers, interrupt handling, register access.\n---\n\n# Architecture Patterns\n\n## ARM Cortex-M (MCU)\n\n```c\n/* NVIC */\n#define NVIC_BASE   0xE000E100U\n#define NVIC_ISER(n) (*(volatile uint32_t *)(NVIC_BASE + (n) * 4U))\n\n#define NVIC_ENABLE_IRQ(irq)  do { NVIC_ISER((irq) >> 5) = (1U << ((irq) & 0x1F)); } while(0)\n\n/* Memory barriers */\n__DMB(); __DSB(); __ISB();\n\n/* ISR */\nvoid __attribute__((interrupt)) TIM2_IRQHandler(void) {\n    volatile uint32_t *irq_flag = (uint32_t *)(TIM2_BASE + FLAG_OFFSET);\n    *irq_flag = 0U;\n    g_ticks++;\n    __DSB();\n}\n```\n\n## ARM Cortex-A (SoC)\n\n```c\n/* GIC */\n#define GICD_BASE  0x1E001000U\n#define GICC_BASE  0x1E000000U\n\n/* SMP barrier */\n__asm volatile (\"dmb ish\" ::: \"memory\");\n\n/* Cache */\n__asm volatile (\"ic iallu\" ::: \"memory\");\n```\n\n## PowerPC (SoC)\n\n```c\n/* SPR access */\nstatic inline uint32_t mfspr(uint16_t spr) {\n    uint32_t val;\n    __asm volatile (\"mfspr %0, %1\" : \"=r\"(val) : \"K\"(spr));\n    return val;\n}\n\n/* Barrier */\n__asm volatile (\"msync\");\n```\n\n## SPARC V8 (Leon3)\n\n```c\n/* PSR */\nstatic inline uint32_t sparc_get_psr(void) {\n    uint32_t psr;\n    __asm volatile (\"rd %%psr, %0\" : \"=r\"(psr));\n    return psr;\n}\n\n/* Barrier */\n__asm volatile (\"stbar\");\n```\n\n## RISC-V\n\n```c\n/* CSR */\n#define CSR_MSTATUS 0x300\n#define CSR_MIE     0x304\n\nstatic inline uint32_t csrr(uint32_t csr) {\n    uint32_t val;\n    __asm volatile (\"csrr %0, %1\" : \"=r\"(val) : \"K\"(csr));\n    return val;\n}\n\n/* Barrier */\n__asm volatile (\"fence\" ::: \"memory\");\n```\n\n## Quick Ref\n\n| Arch | Barrier | Interrupt | SPR/CSR |\n|------|---------|-----------|---------|\n| Cortex-M | `__DMB()` | NVIC | N/A |\n| Cortex-A | `dmb ish` | GIC | N/A |\n| PowerPC | `msync` | PIC | `mfspr` |\n| SPARC V8 | `stbar` | INTC | `rd psr` |\n| RISC-V | `fence` | PLIC | `csrr` |\n\n## 未知架构处理\n\n如果用户提到的架构不在上述列表中:\n\n### 处理步骤\n\n1. **先尝试推断**: 根据用户描述推断架构类型\n2. **尝试网上搜索**: 如果是未知架构,使用WebSearch/WebFetch搜索该架构的基础信息\n3. **使用通用模式**: 如果无法找到信息,使用通用嵌入式C模式\n4. **与用户沟通**: 把学到的架构信息反馈给用户,确认理解是否正确\n\n### 网上搜索流程\n\n当遇到未知架构时:\n\n```\n1. 使用 WebSearch 搜索: \"<架构名> embedded C programming\"\n2. 使用 WebSearch 搜索: \"<架构名> register map memory\"\n3. 使用 WebFetch 获取该架构的官方文档或芯片手册摘要\n4. 分析搜索结果,提取:\n   - 寄存器访问模式\n   - 中断处理方式\n   - 内存屏障指令\n   - 工具链信息\n5. 把学到的信息反馈给用户确认\n```\n\n### 搜索示例\n\n| 用户提到 | 搜索关键词 |\n|----------|-----------|\n| MIPS | \"MIPS embedded C interrupt controller\" |\n| ARC | \"ARC EM or ARC HS interrupt handling\" |\n| Tensilica | \"Tensilica Xtensa register access\" |\n| Andes | \"Andes RISC-V interrupt\" |\n\n### 与用户沟通格式\n\n```markdown\n🤖 **已搜索并学习该架构**\n\n根据搜索结果,我了解到该架构的一些基础信息:\n\n| 特性 | 信息 |\n|------|------|\n| 内存屏障 | 搜索到的指令 |\n| 中断方式 | 搜索到的信息 |\n| 寄存器访问 | 搜索到的模式 |\n\n**请确认以下理解是否正确:**\n1. ...\n2. ...\n\n如果信息有误,请纠正或提供正确的信息。\n```\n\n### 通用模式 (所有架构可用)\n\n```c\n/* 通用寄存器定义 - 架构无关 */\n#define REG32(base, offset)  (*(volatile uint32_t *)((base) + (offset)))\n\n/* 通用内存屏障 - 编译器级别 */\n#define MEMORY_BARRIER()  __asm volatile(\"\" ::: \"memory\")\n\n/* 通用中断使能宏"},{"path":"embedded-code-skill-domains/SKILL.md","content":"---\nname: embed-code-domains\ndescription: Industry domain requirements. Aerospace (DO-178C), Military (MIL-STD), Industrial (IEC 61508), Automotive (ISO 26262).\n---\n\n# Industry Domain Requirements\n\n## Detection\n\n| Domain | Keywords |\n|--------|----------|\n| Aerospace | DO-178C, DAL, ARINC, flight |\n| Military | 1553B, SpaceWire, MIL-STD, radar |\n| Industrial | IEC 61508, SIL, PLC, SCADA |\n| Automotive | ISO 26262, ASIL, CANFD |\n\n---\n\n## Aerospace (DO-178C)\n\n**DAL Levels**: A (MC/DC 100%), B (MC/DC 100%), C (Statement/Branch)\n\n```c\n/**\n * @file navigation.c\n * @brief Navigation processing\n *\n * ### Safety Level: DAL-B ###\n * - DO-178C compliance\n * - MC/DC coverage required\n *\n * ### Software Level Database ###\n * - Req ID: NAV-001\n */\n```\n\n**Requirements**:\n- No dynamic allocation\n- Deterministic behavior\n- No recursion\n- Complexity < 10\n\n---\n\n## Military (MIL-STD-1553B)\n\n```c\n/**\n * @file missile_ctrl.c\n * @brief Missile guidance control\n *\n * ### Standards ###\n * - MIL-STD-1553B\n * - SEU protection required\n * - BIT coverage > 95%\n */\n```\n\n**Requirements**:\n- Hardware redundancy\n- SEU protection\n- BIT diagnostics\n\n---\n\n## Industrial (IEC 61508)\n\n**SIL Levels**: 1, 2, 3, 4\n\n```c\n/**\n * @file plc_comm.c\n * @brief PLC communication\n *\n * ### IEC 61508 SIL-2 ###\n * - Safe state on failure\n * - Diagnostic coverage > 90%\n */\n```\n\n**Requirements**:\n- Safe state defined\n- Watchdog supervision\n- Deterministic response\n\n---\n\n## Automotive (ISO 26262)\n\n**ASIL Levels**: A, B, C, D\n\n```c\n/**\n * @file abs_controller.c\n * @brief ABS control\n *\n * ### ASIL-B ###\n * - ISO 26262 Part 2-6\n * - SPFM > 90%, LFM > 60%\n */\n```\n\n**Requirements**:\n- ASIL decomposition\n- Hardware fault tolerance\n- Freedom from interference\n\n---\n\n## Default (General Embedded)\n\n```c\n/**\n * @file sensor_driver.c\n * @brief Temperature sensor driver\n *\n * ### Architecture ### ARM Cortex-M4\n * ### Domain ### General Embedded\n */\n```\n\nNo special safety requirements.\n\n---\n\n## Quick Ref\n\n| Domain | Standard | Level | Key |\n|--------|----------|-------|-----|\n| Aerospace | DO-178C | DAL-A/B/C | MC/DC |\n| Military | MIL-STD-1553B | - | SEU |\n| Industrial | IEC 61508 | SIL-1-4 | Safe state |\n| Automotive | ISO 26262 | ASIL-A/B | SPFM/LFM |"},{"path":"embedded-code-skill-drivers/SKILL.md","content":"---\nname: embed-code-drivers\ndescription: Peripheral driver templates. UART, SPI, I2C, DMA, CAN, CANFD, PWM, Ethernet, 1553B, SpaceWire, SDIO, Timer, WDT, GPIO.\n---\n\n# Driver Templates\n\n## UART\n\n```c\n#define UART_DR(base)   (*(volatile uint32_t *)((base) + 0x00U))\n#define UART_CR(base)   (*(volatile uint32_t *)((base) + 0x30U))\n#define UART_FR(base)   (*(volatile uint32_t *)((base) + 0x18U))\n\ntypedef struct {\n    uint32_t base_address;\n    uint32_t baud_rate;\n} uart_config_t;\n\ntypedef struct {\n    bool     initialized;\n    uint8_t  rx_buf[256];\n    uint16_t rx_head;\n    uint16_t rx_tail;\n} uart_handle_t;\n```\n\n## SPI\n\n```c\n#define SPI_CR1(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define SPI_SR(base)   (*(volatile uint32_t *)((base) + 0x08U))\n#define SPI_DR(base)   (*(volatile uint32_t *)((base) + 0x0CU))\n\ntypedef struct {\n    uint32_t base_address;\n    uint32_t clock_hz;\n    bool     master_mode;\n} spi_config_t;\n```\n\n## I2C\n\n```c\n#define I2C_CR1(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define I2C_DR(base)   (*(volatile uint32_t *)((base) + 0x10U))\n#define I2C_SR1(base)  (*(volatile uint32_t *)((base) + 0x14U))\n```\n\n## DMA\n\n```c\n#define DMA_CCR(base,ch)  (*(volatile uint32_t *)((base) + 0x08U + (ch) * 0x14U))\n#define DMA_CPAR(base,ch) (*(volatile uint32_t *)((base) + 0x10U + (ch) * 0x14U))\n#define DMA_CMAR(base,ch) (*(volatile uint32_t *)((base) + 0x14U + (ch) * 0x14U))\n```\n\n## CAN\n\n```c\n#define CAN_MCR(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define CAN_TSR(base)  (*(volatile uint32_t *)((base) + 0x08U))\n#define CAN_BTR(base)  (*(volatile uint32_t *)((base) + 0x1CU))\n\ntypedef struct {\n    uint32_t id;\n    uint8_t  dlc;\n    uint8_t  data[64];\n} can_msg_t;\n```\n\n## GPIO\n\n```c\n#define GPIO_MODER(base)  (*(volatile uint32_t *)((base) + 0x00U))\n#define GPIO_ODR(base)   (*(volatile uint32_t *)((base) + 0x14U))\n#define GPIO_BSRR(base)  (*(volatile uint32_t *)((base) + 0x18U))\n\ntypedef enum {\n    GPIO_MODE_INPUT = 0,\n    GPIO_MODE_OUTPUT,\n    GPIO_MODE_AF,\n    GPIO_MODE_ANALOG\n} gpio_mode_t;\n```\n\n## TIMER/WDT\n\n```c\n#define TIM_CR1(base)   (*(volatile uint32_t *)((base) + 0x00U))\n#define TIM_ARR(base)   (*(volatile uint32_t *)((base) + 0x2CU))\n#define TIM_CNT(base)   (*(volatile uint32_t *)((base) + 0x24U))\n\n#define WDT_KR(base)   (*(volatile uint32_t *)((base) + 0x00U))\n#define WDT_RLR(base)  (*(volatile uint32_t *)((base) + 0x08U))\n```\n\n## 1553B\n\n```c\ntypedef enum {\n    1553_MODE_BC = 0,\n    1553_MODE_RT = 1,\n    1553_MODE_BM = 2\n}1553_mode_t;\n\ntypedef struct {\n    uint8_t  cmd;\n    uint16_t status;\n    uint16_t data[32];\n}1553_msg_t;\n```"},{"path":"embedded-code-skill-standards/SKILL.md","content":"---\nname: embed-code-standards\ndescription: Embedded C coding standards reference. Naming conventions, type standards, error handling, struct/enum patterns, comment rules.\n---\n\n# Coding Standards\n\n## Naming\n\n| Element | Convention | Example |\n|---------|------------|---------|\n| Variables | snake_case | `sensor_value` |\n| Globals | g_snake_case | `g_system_ticks` |\n| Constants | SCREAMING_SNAKE | `MAX_BUFFER_SIZE` |\n| Macros | SCREAMING_SNAKE | `GPIO_MODE_INPUT` |\n| Functions | camelCase | `initUart()` |\n| Struct types | snake_case_t | `uart_config_t` |\n| Enum types | snake_case_t | `gpio_state_t` |\n| Enum values | PREFIXED_SNAKE | `GPIO_STATE_LOW` |\n| Pointers | p_snake_case | `p_rx_buffer` |\n\n## Types\n\nUse only stdint.h types:\n\n```\nuint8_t  → byte, GPIO\nuint16_t → 16-bit registers\nuint32_t → 32-bit registers\nint32_t  → signed values\nbool     → flags\n```\n\n**NEVER**: int, char, long (unless necessary)\n\n## Includes (Required)\n\n```c\n#include <stdint.h>\n#include <stdbool.h>\n#include <stddef.h>\n```\n\n## Error Handling\n\n```c\ntypedef enum {\n    EmbedCode_Ok = 0,\n    EmbedCode_ErrNullPtr = -1,\n    EmbedCode_ErrInvalidArg = -2,\n    EmbedCode_ErrTimeout = -3,\n    EmbedCode_ErrBusy = -4\n} embed_code_status_t;\n\n#define VALIDATE_NOT_NULL(ptr) \\\n    do { if ((ptr) == NULL) return EmbedCode_ErrNullPtr; } while(0)\n```\n\nEvery public function:\n- Returns `embed_code_status_t`\n- Validates NULL pointers\n- Returns specific error codes\n\n## Struct Patterns\n\n```c\n// Config - const after init\ntypedef struct {\n    uint32_t base_address;\n    uint8_t  priority;\n} peripheral_config_t;\n\n// Handle - runtime state\ntypedef struct {\n    bool                initialized;\n    peripheral_config_t config;\n} peripheral_handle_t;\n\n// State enum\ntypedef enum {\n    STATE_IDLE = 0,\n    STATE_RUNNING,\n    STATE_ERROR\n} state_t;\n```\n\n## No Dynamic Allocation\n\n**PROHIBITED**: malloc, free, calloc, realloc, new, delete, VLAs\n\n**ALWAYS**: Fixed-size buffers\n\n```c\n#define BUFFER_SIZE 256U\nuint8_t buffer[BUFFER_SIZE];\n```\n\n## Comments\n\n**语言: 优先使用中文**\n\n```c\n// ✅ 正确 - 使用中文注释,解释 WHY\nconfig |= (1U << 3);  /* 低电平有效 */\n\n// ❌ 错误 - 使用英文注释\nconfig |= (1U << 3);  /* Active-low enable */\n\n// ❌ 错误 - 解释代码本身已清楚表达的内容\ni++;  /* i 自增 */\n```\n\n**注释原则:**\n- **中文优先**: 便于团队阅读和维护\n- **解释 WHY**: 说明原因和意图,而非描述代码在做什么\n- **代码自说明**: 如果代码本身已清楚表达含义,无需注释\n\n## Quality Checklist\n\n- [ ] stdint.h types only\n- [ ] Naming correct\n- [ ] Public functions return status\n- [ ] NULL validation\n- [ ] No magic numbers\n- [ ] Comments explain WHY\n- [ ] No malloc/free"},{"path":"SKILL.md","content":"---\nname: embedded-code-skill\ndescription: \"Generate, rewrite, or review embedded C code. Use when creating/rewriting/reviewing embedded C for microcontrollers, drivers, firmware. Triggers automatically when user mentions: generate, create, write code, implement driver, rewrite, refactor, review, check, audit.\"\nuser-invocable: true\n---\n\n# Embedded C 代码生成规范\n\n## 概述\n\n本规范用于生成生产级嵌入式 C 代码，适用于 STM32、PowerPC、RISC-V 等平台。\n\n**核心原则**: 像嵌入式软件架构师一样思考，生成可演进、可测试、可移植的代码。\n\n---\n\n## 思维方式\n\n生成代码时必须以**嵌入式软件架构师**的思维进行:\n\n| 维度 | 要求 |\n|------|------|\n| **系统视角** | 设计可演进的系统，考虑模块边界、接口契约、依赖关系 |\n| **资源意识** | 内存精确计算缓冲区，CPU 减少中断嵌套，优化关键路径 |\n| **实时性** | ISR 应尽可能短，考虑 WCET，防范优先级反转/死锁/队列溢出 |\n| **可靠性** | 看门狗策略、异常恢复、关键数据冗余存储 |\n| **硬件无关** | 寄存器抽象为结构体，驱动与业务逻辑分离 |\n| **可测试** | 公共接口易 mock，状态机可单步测试，边界条件覆盖 |\n\n---\n\n## 编码规范\n\n### 1. 类型规范\n\n| 类型 | 用途 | 禁止 |\n|------|------|------|\n| `uint8_t` | 单字节、GPIO | `char`, `signed char` |\n| `uint16_t` | 16位寄存器 | `short`, `unsigned short` |\n| `uint32_t` | 32位寄存器、时间戳 | `int`, `long`, `unsigned int` |\n| `int32_t` | 有符号值 | - |\n| `uint64_t` | 64位数据 | - |\n| `bool` | 布尔标志 | - |\n\n**必须包含的头文件:**\n```c\n#include <stdint.h>\n#include <stdbool.h>\n#include <stddef.h>\n```\n\n### 2. 命名规范\n\n| 元素 | 格式 | 示例 |\n|------|------|------|\n| 变量 | `snake_case` | `sensor_value`, `data_count` |\n| 全局变量 | `g_snake_case` | `g_system_ticks` |\n| 常量/宏 | `SCREAMING_SNAKE` | `MAX_BUFFER_SIZE`, `SPI_CR_EN` |\n| 函数 | `camelCase` | `initUart()`, `getSensorData()` |\n| 结构体类型 | `snake_case_t` | `uart_config_t` |\n| 枚举类型 | `snake_case_t` | `gpio_state_t` |\n| 枚举值 | `PREFIXED_SNAKE` | `GPIO_STATE_LOW` |\n| 指针 | `p_snake_case` | `p_rx_buffer` |\n| 寄存器结构体 | `module_name_reg_t` | `spi_reg_t` |\n| 寄存器头文件 | `module_reg.h` | `spi_reg.h` |\n\n### 3. 错误处理\n\n所有 public 函数必须:\n\n1. 返回 `embedded_code_status_t` 枚举类型\n2. 验证所有输入指针（NULL 检查）\n3. 返回具体错误码\n\n```c\ntypedef enum {\n    EmbedCode_Ok = 0,\n    EmbedCode_ErrNullPtr = -1,\n    EmbedCode_ErrInvalidArg = -2,\n    EmbedCode_ErrTimeout = -3,\n    EmbedCode_ErrBusy = -4,\n    EmbedCode_ErrNotInit = -5\n} embedded_code_status_t;\n\n#define VALIDATE_NOT_NULL(ptr) \\\n    do { if ((ptr) == NULL) return EmbedCode_ErrNullPtr; } while(0)\n```\n\n### 4. 注释规范\n\n**注释语言: 优先使用中文**\n\n| 原则 | 说明 |\n|------|------|\n| **中文优先** | 便于团队阅读和维护 |\n| **解释 WHY** | 注释应说明原因和意图，而非描述代码在做什么 |\n| **代码自说明** | 如果代码本身已清楚表达含义，无需注释 |\n\n**Doxygen 文件头格式:**\n```c\n/**\n * @file spi_reg.h\n * @brief SPI 寄存器结构体定义\n * @author Claude Code\n * @date 2026-04-10\n */\n```\n\n**行内注释示例:**\n```c\nconfig |= SPI_CR_EN_MASK;  /* 启用 SPI，低电平有效 */\n```\n\n### 5. 寄存器结构体定义\n\n**每个外设模块必须有独立的 reg.h 文件:**\n\n| 必需元素 | 说明 |\n|----------|------|\n| `XXX_BASE_ADDR` | 基地址定义，格式：`XXX_BASE_ADDR` |\n| `xxx_reg_t` | 寄存器结构体，使用 `volatile uint32_t` |\n| `XXX_XXX_MASK/SHIFT` | 位字段宏定义 |\n| `XXX_REG` | 结构体指针访问宏 |\n\n**reg.h 模板:**\n```c\n/**\n * @file spi_reg.h\n * @brief SPI 外设寄存器定义\n */\n#ifndef SPI_REG_H\n#define SPI_REG_H\n\n#include <stdint.h>\n\n/* 基地址 */\n#define SPI_BASE_ADDR  (0xA0010000U)\n\n/* 寄存器结构体 */\ntypedef struct {\n    volatile uint32_t CTRL;     /* 0x00: 控制寄存器 */\n    volatile uint32_t STATUS;   /* 0x04: 状"}],"languages":[],"docsSourceLabel":"CLAWHUB","editorialOverview":"Generate, rewrite, or review embedded C code. Use when creating/rewriting/reviewing embedded C for microcontrollers, drivers, firmware. Triggers automaticall... Skill: Embedded Code Skill Owner: leon-2050 Summary: Generate, rewrite, or review embedded C code. Use when creating/rewriting/reviewing embedded C for microcontrollers, drivers, firmware. Triggers automaticall... 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